1. Field of the Invention
The present invention relates to MOS transistors and methods for fabricating the transistors. More particularly, the invention relates to MOS transistors having multiple finger gate structures and capable of operating at high frequencies.
2. Description of the Related Art
High frequency wireless MOS technology for gate lengths below 0.5.mu. is an emerging technology. Devices having gate lengths of 0.3.mu. and 0.1.mu. with intrinsic cut-off frequencies f.sub.t as high as 10 GHz and 60 GHz, respectively, have been reported in the literature.
Two device characteristics are particularly important for high frequency wireless MOS transistors. The intrinsic cut off frequency, f.sub.t, can be represented as: EQU f.sub.t =g.sub.m /[2.pi.(C.sub.gs +C.sub.gd)],
where g.sub.m =transconductance of the MOS transistor, C.sub.gs =signal gate-to-source capacitance, C.sub.gd =signal gate-to-drain capacitance.
Another important variable for high frequency transistors is f.sub.max, the maximum frequency of oscillation (the frequency at which a device can amplify the power of a signal). Maximum frequency, f.sub.max, is defined as: EQU f.sub.max =f.sub.t /2[2.pi.f.sub.t C.sub.gd +g.sub.o (R.sub.g +R.sub.s)].sup.1/2,
where g.sub.o =output conductance, R.sub.g =total gate resistance and R.sub.s =source resistance.
For a given CMOS technology, based on these relationships, the only way to increase f.sub.max is to make the term [2.pi.f.sub.t C.sub.gd +g.sub.o (R.sub.g +R.sub.s)] less than 1. From this relationship, it can be seen that reducing C.sub.gs and C.sub.gd (overlap of drain and source regions under the gate) is desirable. However, conventional MOS technology uses "Light-Doped Drain" (LDD) technology to minimize adverse effects of hot carriers on device reliability, leading to typical values of C.sub.gs +C.sub.gd in the range of 60 fF for 0.35.mu.-0.5.mu. technologies.
Thus, the only option is to minimize the total gate resistance R.sub.g. FIG. 1 graphically represents f.sub.max calculated as a function of R.sub.g. Until R.sub.g is less than 100 .OMEGA., f.sub.max is smaller than f.sub.t, being limited by R.sub.g. For a 0.35.mu. gate with resistivity of 30 .OMEGA./sq, a total gate width W of 20.mu. will lead to R.sub.g =1700 .OMEGA.!
Most FETs used in a CMOS VLSI chip have a straight gate electrode and rectangular source and drain diffused areas on either side of the gate. The source and drain areas are contacted by metal conductors at many locations along the device width. Other FET configurations are known. For example, the literature reports a wide FET in which the gate appears to be in a serpentine pattern and is "driven" only from one end. There is no shorting of the entire gate area.
It is therefore desirable to provide MOS transistors with reduced gate resistance and drain/source-to-gate overlap capacitance.